1. Field of the Invention
The disclosure relates generally to a page buffer for a NAND flash memory, and more particularly to a page buffer of a NAND flash memory for reducing the number of transistors.
2. Description of the Related Art
Flash memory devices are generally classified into NOR flash memories and NAND flash memories. In NOR flash memories, the memory cells are connected in parallel to bit lines, resembling the parallel connection of transistors in CMOS NOR gates, and thus are known as NOR flash memory. The memory cells in NOR flash memories can be randomly accessed. Thus NOR flash memories are mainly used in the BIOS of personal computers, or in firmware for ASIC. The memory cells in NAND flash memories, on the other hand, are connected in series resulting a smaller cell size than that of the NOR flash memories. Thus, NAND flash can provide a smaller die size and faster write and read time than NOR flash. However, the memory cells in NAND flash memories cannot be randomly accessed. Therefore, NAND flash memories are mainly used in storage devices, such as hard disks or memory cards.
Each memory cell in a NAND flash memory resembles a standard MOSFET, except that there is a floating gate below the control gate of each memory cell, wherein the floating gate is isolated by an oxide layer. Electrons placed on the floating gate will be trapped for years, modifying the threshold voltage of the cell. A traditional single layer cell (SLC) of a NAND flash memory may have a normal threshold voltage or a modified threshold voltage, and therefore provides two states, i.e., one bit, for the NAND flash memory. Recently, to increase the integration of memory cells of NAND flash memories, multi-level cells (MLC), which provide more than one bit for the NAND flash memory, and therefore exhibit multiple threshold voltages, have been widely utilized in NAND flash memories.
However, in a NAND flash memory, the size of a page buffer does not matter at high density, but it does at low density, such as 64M bit, 128M bit, 256M bit, or 1G bit. In order to lower the chip size of a low-density NAND flash memory, we need a more effective page buffer circuit with fewer transistors to make the chip size smaller.